Alignment of work pieces is critical to precision semi-conductor device manufacturing. The workpiece may be a so-called wafer. Silicon dioxide is a common wafer material, but other substrates such as gallium arsenide are also used. The workpiece needs to be precisely aligned during manufacturing. For instance, in direct writing to a substrate, the position of the substrate must be determined precisely so that patterning of one layer on top of the next will create the desired three-dimensional structures. For writing in a stepper, a mask must be precisely aligned with the workpiece. For patterning a complex mask, such as a phase shift mask, the position of the workpiece must be precisely determined so that the phase shift areas will be positioned properly in relationship to un-shifted areas of the mask.
Alignment marks typically are formed on a workpiece to assist with alignment. The spaces between chips or around the perimeter of a wafer are available for placement of alignment marks. Some equipment manufacturers, such as Nikon, favor elevated structures for alignment. Others, such as ASML, favor trenches. Alignment marks may be structures on or in the workpiece by depositing some material. Formed structures may be of a material similar to the underlying or may be strongly contrasting, such as copper on an oxide of silicon or a glass material. Contrasting colors may result from contrasting materials or from thin films.
Some manufacturing processes, such as chemical-mechanical planarization (CMP), can erode an alignment mark. Ideally, CMP flattens the surface of a wafer without any bias. However, as with a saw that cuts deeper on the push stroke than the pull stroke, CMP sometimes will remove one edge of a mark more than another edge. Even without bias, a mark that lands in a relative high area of a wafer may be abraded across the entire mark.
Other manufacturing processes, such as forming an oxide or glass layer, or applying resist may cover or obscure an alignment mark. Manufacturing of chips increasingly involves creation of multi-layer structures. Structures are becoming increasingly vertical, as efforts are made to shrink feature sizes and condense features into smaller areas. Layering of structures on a wafer tends to obscure alignment marks or, in signal processing terms, reduce the signal that an alignment system is trying to detect. In some instances, very faint marks may be desirable.
Accordingly, an opportunity arises to introduce new methods of and devices for precise alignment of work pieces, including wafers and reticles.